Detailed Description

The MAX77960/MAX77961 are highly flexible, highly integrated switch mode charger. Autonomous charging inputs configure the charger without host I²C interface, see the Autonomous Charging section for more details. The MAX77960/MAX77961 have an I²C interface that allows the host controller to program and monitor the charger. Charger configuration registers, interrupt, interrupt mask, and status registers are described in the Register Map.

The CNFG is the MAX77960/MAX77961's configuration input for the number of battery cells in series connection (2S or 3S).

Connect a resistor (R_CNFG) from CNFG to GND to program. See Table 1.

The host can reduce the MAX77960/MAX77961's CHGIN supply current by driving STBY pin to high or setting STBY_EN bit to 1. When STBY is pulled high or STBY_EN bit is set to 1, the DC-DC turns off. When STBY is pulled low and STBY_EN bit is set to 0, the DC-DC is controlled by the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ.

The host can disable the Q_BAT switch by setting DISIBS bit to 1 or driving DISQBAT pin to high. Charging stops when Q_BAT switch is disabled.

When DISQBAT is pulled low and DISIBS bit is set to 0, Q_BAT FET control is defined in Table 2. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ.

The Q_BAT control and the DC-DC control depend on both hardware pins (OTGEN, DISQBAT, and STBY) and their associated I²C registers.

The thermistor input can be utilized to achieve functions include charge suspension, JEITA-compliant charging and battery removal detection. Thermistor monitoring feature can be disabled by connecting the THM pin to ground.

Charge Suspension

The THM input connects to an external negative temperature coefficient (NTC) thermistor to monitor battery or system temperature. Charging stops when the thermistor temperature is out of range (T < T_COLD or T > T_HOT). The charge timers are reset and the CHG_DTLS[3:0], CHG_OK register bits report the charging suspension status and CHG_I interrupt bit is set. When the thermistor comes back into range (T_COLD < T < T_HOT), charging resumes and the charge timer restarts.

JEITA-Compliant Charging

JEITA-compliant charging is available with JEITA_EN = 1. See the JEITA Compliance section for more details.

Battery Removal Detection

Connecting THM to AVL emulates battery removal and prevents charging.

Disable Thermistor Monitoring

Connecting THM to GND disables the thermistor monitoring function, and JEITA-controlled charging is unavailable in this configuration. The MAX77960/MAX77961 detect an always-connected battery when THM is grounded, and charging starts automatically when a valid adapter is plugged in. In applications with removable batteries, do not connect THM to GND because the MAX77960/MAX77961 cannot detect battery removal when THM is grounded. Instead, connecting THM to the thermistor pin in the battery pack is recommended.

Since the thermistor monitoring circuit employs an external bias resistor from THM to AVL, the thermistor is not limited only to 10kΩ (at +25ºC). Any resistance thermistor can be used as long as the value is equivalent to the thermistors +25ºC resistance. For example, with a 10kΩ at R_TB resistor, the charger enters a temperature suspend state when the thermistor resistance falls below 3.97kΩ (too hot) or rises above 28.7kΩ (too cold). This corresponds to 0ºC to +50ºC range when using a 10kΩ NTC thermistor with a beta of 3500. The general relation of thermistor resistance to temperature is defined by the following equation:

$R_T=R_{25}x{\mathit{e}}^{\{\mathrm{\beta x}(\frac{1}{T+273°C}-\frac{1}{298°C})\}}$

where:

R_T = The resistance in Ω of the thermistor at temperature T in Celsius

R₂₅ = The resistance in Ω of the thermistor at +25ºC

β = The material constant of the thermistor, which typically ranges from 3000k to 5000k

T = The temperature of the thermistor in °C

Some designs might prefer other thermistor temperature limits. Threshold adjustment can be accommodated by changing R_TB, connecting a resistor in series and/or in parallel with the thermistor, or using a thermistor with different β. For example, a +45ºC hot threshold and 0°C cold threshold can be realized by using a thermistor with a β to 4250 and connecting 120kΩ in parallel. Since the thermistor resistance near 0ºC is much higher than it is near +50ºC, a large parallel resistance lowers the cold threshold, while only slightly lowering the hot threshold. Conversely, a small series resistance raises the cold threshold, while only slightly raising the hot threshold. Raising R_TB raises both the hot and cold threshold, while lowering R_TB lowers both thresholds.

Since AVL is active whenever a valid input power is connected at DC, thermistor bias current flows at all times, even when charging is disabled. When using a 10kΩ thermistor and a 10kΩ pullup to ADCREF, this results in an additional 250μA load. This load can be reduced to 25μA by instead using a 100kΩ thermistor and 100kΩ pullup resistor.

The MAX77960/MAX77961 support autonomous charging without I²C. In applications without I²C serial communication, use the following pins to configure the MAX77960/MAX77961 charger:

CNFG, INLIM, ITO, ISET, VSET, OTGEN, DISQBAT, STBY.

The INLIM, ITO, ISET, and VSET pins are used to program the charger's input current limit, top-off current, constant charging current, and termination voltage.

Connect a valid resistor from each of these pins to ground to program the charger. See the Pin Description for details.

Connect all four pins (INLIM, ITO, ISET, VSET) to PVL to use the default values for the associated charger registers.

For autonomous charging, it is considered an abnormal condition if some of these pins (INLIM, ITO, ISET, VSET) connect to a valid resistor, but others do not (for example open or connects to PVL or connects to a resistor that is out of range). When this happens, the MAX77960/MAX77961 allow the DC-DC to switch and regulate the SYS voltage, but disable charging for safety reasons. The STAT pin reports no charge.

When a valid charge source is applied to CHGIN, the MAX77960/MAX77961 limit the current drawn from the charge source to the value programmed with INLIM pin.

The default charger input current limit is programmed with the resistance from INLIM to GND. See Table 5.

If I²C is used in the application, the CHGIN input current limit can also be reprogrammed with CHGIN_ILIM[6:0] register bits after the devices power up. Connect INLIM pin to PVL to use I²C default settings.

When a valid input source is present, the battery charger attempts to charge the battery with a fast-charge current programmed with ISET pin.

The default fast-charge current is programmed with the resistance from ISET to GND. See Table 6.

If I²C is used in the application, the fast-charge current can also be reprogrammed with CHGCC[5:0] register bits after the devices power up. Connect ISET pin to PVL to use I²C default settings.

When the battery charger is in the top-off state, the top-off charge current is programmed by ITO pin.

The default top-off charge current is programmed with the resistance from ITO to GND. See Table 7.

If I²C is used in the application, the top-off current can also be reprogrammed with TO_ITH[2:0] register bits after the device powers up. Connect ITO pin to PVL to use I²C default settings.

The default charge termination voltage is programmed with the resistance from VSET to GND. See Table 8.

If I²C is used in the application, the charge termination voltage can also be reprogrammed with CHG_CV_PRM[5:0] register bits after the device powers up. Connect the VSET pin to PVL to use I²C default settings.

The MAX77960/MAX77961 feature a switch mode buck-boost charger for a two-cell or three-cell lithium ion (Li+) or lithium polymer (Li-polymer) battery. The charger operates from a wide input range from 3.5V to 25.4V, ideal for USB-C charging applications. The charger input current limit is programmable from 100mA to 3.15A (MAX77960)/100mA to 6.3A (MAX77961), which is flexible to operate from either an AC-to-DC wall charger or a USB-C adapter.

The MAX77960/MAX77961 offer a high level of integration and do not require any external MOSFETs to operate, which significantly reduces the solution size. They operate with a fixed switching frequency of 600kHz. The battery charging current is programmable from 100mA to 3A (MAX77960)/100mA to 6A (MAX77961) to accommodate small or large capacity batteries.

When the input source is not available, the MAX77960/MAX77961 can be enabled in a reverse buck mode, delivering energy from the battery to the input, CHGIN, commonly known as USB on-the-go (OTG). In OTG mode, the regulated CHGIN voltage is 5.1V with programmable current limit up to 3A.

Maxim’s Smart Power Selector architecture makes the best use of the limited adapter power and the battery power to power the system. Adapter power that is not used for the system charges the battery. When system load exceeds the input limit, battery provides additional current to the system up to the BAT to SYS overcurrent threshold, programmable with B2SOVRC[3:0] I²C register bits. All power switches for charging and switching the system load between battery and adapter power are integrated on chip—no external MOSFETs required.

Maxim’s proprietary process technology allows for low-R_DSON devices in a small solution size. The resistance between BAT to SYS is 10mΩ (typ), allowing low power dissipation and long battery life.

A multitude of safety features ensure reliable charging. Features include charge timers, watchdog, junction thermal regulation, and over-/undervoltage protection.

The smart power selector (SPS) architecture includes a network of internal switches and control loops that efficiently distributes energy between an external power source (CHGIN), the battery (BAT) and the system (SYS). This architecture allows power path operation with system instant on with a dead battery.

The Simplified Block Diagram shows the smart power selector switches and gives them the following names: Q_1, Q₂, Q₃, Q₄ and Q_BAT.

Power Switches and Current Sense Resistor Descriptions

• CHGIN Current-Sense Resistor: As shown in the Simplified Block Diagram, the CHGIN current is monitored with the input current sensing resistor, R_S1, connected between CSINP and CSINN pins.
• DC-DC Switches: Q_1, Q₂, Q₃, and Q₄ are the DC-DC switches that can operate as a buck (step down) or a boost (step up), depending on the external power source and battery voltage conditions.
• Battery-to-System Switch: Q_BAT is used to control battery charging and discharging operations.

I²C Configuration Register Bits

• MODE[3:0] configures the Smart Power Selector mode to be Charging, OTG or DC-DC mode respectively. See MODE[3:0] register bits in the Register Map for details.
• VCHGIN_REG[4:0] sets the CHGIN regulation voltage, when the MAX77960/MAX77961 operate in forward mode (CHGIN has a valid power source). See the CHGIN Regulation Voltage section for details.
• MINVSYS[2:0] sets the minimum system regulation voltage. See the SYS Regulation Voltage section for details.
• B2SOVRC[3:0] sets the battery to system discharge overcurrent protection threshold.

Energy Distribution Priority

• With a valid external power source at CHGIN:
  • The external power source is the primary source of energy.
  • The battery is the secondary source of energy.
  • Energy delivery to SYS has the highest priority.
  • Any remaining energy from the power source that is not required by the system is available to the battery charger.
• With no valid external power source at CHGIN:
  • The battery is the primary source of energy.
  • When OTG mode is enabled, energy delivery to SYS has the highest priority.
  • Any remaining energy from the battery that is not required by the system is available to power the CHGIN.

• In forward mode (when CHGIN is powered from a valid external source), CHGIN voltage is regulated to VCHGIN_REG[4:0] when a high impedance or current limited source is applied. VCHGIN might experience significant voltage droop from the high-impedance source when the MAX77960/MAX77961 extract high power from the source. Regulating VCHGIN allows the MAX77960/MAX77961 to extract the most power from the power source. See the Adaptive Input Current Limit (AICL) and Input  Voltage Regulation section for more detail.
• In reverse mode (OTG), CHGIN voltage is regulated to 5.1V with programmable current limit up to 3A (OTG_ILIM[2:0]).

With a valid external power source at CHGIN:​

• When the DC-DC is disabled (MODE[3:0] = 0x00 or STBY_EN = 0b1 or STBY pin = high), the Q_BAT switch is fully on and V_SYS = V_BATT - I_BATT x R_BAT2SYS.

• When the DC-DC is enabled and the charger is disabled (MODE[3:0] = 0x04), V_SYS is regulated to V_BATTREG (CHG_CV_PRM) and Q_BAT is off.
• When the DC-DC is enabled and the charger is enabled (MODE[3:0] = 0x05), but in a noncharging state such as Done, Thermistor Suspend, Watchdog Suspend, or Timer Fault, V_SYS is regulated to V_BATTREG (CHG_CV_PRM) and Q_BAT is off.
• When the DC-DC is enabled and the charger is enabled (MODE[3:0] = 0x05) and in a valid charging state such as Precharge or Trickle Charge (V_BATT < V_SYSMIN - 500mV), V_SYS is regulated to V_SYSMIN. The charger operates as a linear regulator, and the power dissipation can be calculated with P = (V_SYSMIN - V_BATT) x I_BATT.
• When the DC-DC is enabled and the charger is enabled (MODE[3:0] = 0x05) and in a valid charging state such as Fast Charge (CC or CV) or Top-Off (V_BATT > V_SYSMIN - 500mV), the Q_BAT switch is fully on, and V_SYS = V_BATT + I_BATT x R_BAT2SYS.
• In all the modes described above when the power demand on SYS exceeds the input source power limit, the battery automatically provides supplemental power to the system. If the Q_BAT switch is initially off when V_SYS drops to V_BATT - V_BSREG, the Q_BAT switch turns on, and V_SYS is regulated to V_BATT - V_BSREG.

Without a valid external power source at CHGIN, including with OTG mode (MODE[3:0] = 0x0A):

• The Q_BAT switch is fully on, and V_SYS = V_BATT - I_BATT x R_BAT2SYS.

The MAX77960/MAX77961 transition between power states as input/battery and load conditions dictate.

The MAX77960/MAX77961 provide four (4) power states and one (1) no power state. Under power limited conditions, the power path feature maintains SYS and USB-OTG loads at the expense of battery charge current. In addition, the battery supplements the input power when needed. See the Smart Power Selector (SPS) section for more details. As shown, transitions between power states are initiated by detection/removal of valid power sources, OTG events, and undervoltage conditions.

1. NO INPUT POWER, MODE[3:0] = undefined: No input adapter or battery is detected. The charger and system are off. Battery is disconnected.

2. BATTERY-ONLY, MODE[3:0] = any mode: CHGIN is invalid or outside the input voltage operating range. Battery is connected to power the SYS load (Q_BAT = on).

3. NO CHARGE - DC-DC in FORWARD mode, MODE[3:0] = 0x04: CHGIN input is valid, DC-DC supplies power to SYS. DC-DC operates from a valid input. Battery is disconnected (Q_BAT = off) when SYS load is less than the power that DC-DC can supply.

4. CHARGE - DC-DC in FORWARD mode, MODE[3:0] = 0x05: CHGIN input is valid, DC-DC supplies power to SYS and charges the battery with IBATT. DC-DC operates from a valid input.

5. OTG - DC-DC in REVERSE mode (OTG), MODE[3:0] = 0x0A: OTG is active. Battery is connected to support SYS and OTG loads (Q_BAT = on), and charger operates in REVERSE buck mode.

The MAX77960/MAX77961's default power state is CHARGE - DC-DC in FORWARD mode, MODE[3:0] = 0x05. For battery authentication/safety purposes, the MAX77960/MAX77961 can be configured to keep charging disabled while allowing the DC-DC to switch and regulate the SYS voltage when power is applied to CHGIN. To implement this and enable the charger when appropriate:

• Connect at least one of the INLIM, ITO, ISET or VSET pins to a valid resistor while tying the others (at least one) to PVL. CHG_DTLS = 0x05 and CHG_OK = 0.
• The system processor can configure the charger through the I²C interface.
• The system processor enables charging by setting COMM_MODE to 1 (default is 0).

See Wide-Input I²C Programmable Charger with Charger Disabled for a pin connection example. Pin INLIM is connected to a valid resistor while ITO, ISET and VSET tie to PVL. The default input current limit is programmed by R_INLIM, while default top-off current, constant charging current, and termination voltage use their default value. The system processor can re-program all four settings through the I²C interface if needed.

The charger input is compared with several voltage thresholds to determine if it is valid. A charger input must meet the following characteristics to be valid:

• CHGIN must be above V_{CHGIN_UVLO} to be valid. Once CHGIN is above UVLO threshold, the information is latched and can only be reset when charger is in adaptive input current loop (AICL) and input current is lower than IULO threshold of 30mA.
• CHGIN must be below its overvoltage lockout threshold (V_{CHGIN_OVLO}).

The devices generate a CHGIN_I interrupt (maskable with CHGIN_M bit) when the CHGIN status changes. Read the CHGIN input status with CHGIN_OK and CHGIN_DTLS[1:0] register bits.

The MAX77960/MAX77961 feature input power management to extract maximum input power while avoiding input source overload. The adaptive input current limit (AICL) and the input voltage regulation (CHGIN_REG) features allow the charger to extract more energy from relatively high resistance charge sources with long cables, noncompliant USB hubs or current limited adapters. In addition, the input power management allows the MAX77960/MAX77961 to perform well with adapters that have poor transient load responses.

With a high-resistance source, the charger input voltage drops substantially when it draws large current from the source. The charger's input voltage regulation loop automatically reduces the current drawn from the input to regulate the input voltage at V_{CHGIN_REG}. If the input current is reduced to I_{CHGIN_REG_OFF} (50mA typ) and the input voltage is still below V_{CHGIN_REG}, the charger input turns off. V_{CHGIN_REG} is programmable with VCHGIN_REG[4:0] register bits.

With a current limited source, if the MAX77960/MAX77961’s input current limit is programmed above the current limit of the adapter, the charger input voltage starts to drop when the input current drawn exceeds the source current limit. The charger's input voltage regulation loop allows the MAX77960/MAX77961 to reduce its input current and operate at the current limit of the adapter.

When operating with the input voltage regulation loop active, an AICL_I interrupt is generated, AICL_OK sets to 0. The device prioritize system energy delivery over battery charging. See the Smart Power Selector (SPS) section for more details.

To extract most input power from a current limited charge source, monitor the AICL_OK status while decreasing the CHGIN_ILIM[6:0] register setting. Setting the CHGIN_ILIM[6:0] to a reduced to a value below the current limit of the adapter causes the input voltage to rise. Although the CHGIN_ILIM[6:0] is lowered, more power can be extracted from the adapter when the input voltage rises.

To ensure that a rapid removal and reinsertion of a charge source always results in a charger input interrupt, the charger input presents loading to the input capacitor to ensure that when the charge source is removed, the input voltage decays below the UVLO threshold in a reasonable time (t_INSD). The input self-discharge is implemented by with a 44kΩ resistor (R_INSD) from CHGIN input to ground.

To ensure a timely, complete, repeatable, and reliable reset behavior when the system has no power, the MAX77960/MAX77961 actively discharge the BATT and SYS nodes when the adapter is missing, the battery is removed and V_SYS is less than V_SYSUVLO. The BATT and SYS discharge resistors are both 600Ω.

The MAX77960/MAX77961 utilize several charging states to safely and quickly charge batteries as shown in Figure 1 and Figure 2. Figure 1 shows an exaggerated view of a Li+/Li-Poly battery progressing through the following charge states when there is no system load and the die and battery are close to room temperature:  Prequalification → Fast-charge → Top-off → Done.

From any state shown in Figure 2 except thermal shutdown, the no input power or charger disabled state is entered whenever the charger is programmed to be off or the charger input CHGIN is invalid. After being in this state for t_SCIDG, CHG_DTLS is set to 0x08 and CHG_OK is set to 1. A CHG_I interrupt is generated if CHG_OK was 0 previously.

While in the no input power or charger disabled state, the charger current is 0mA, the watchdog and charge timers are forced to 0, and the power to the system is provided by either the battery or the adapter. When both battery and adapter power are available, the adapter provides primary power to the system and the battery contributes supplemental energy to the system if necessary.

To exit the no input power or charger disabled state, the charger input must be valid and the charger must be enabled.

As shown in Figure 2, the charger enters the precharge state when the battery voltage is less than V_PRECHG. After being in this state for t_SCIDG, a CHG_I interrupt is generated if CHG_OK was 0 previously, CHG_OK is set to 1 and CHG_DTLS is set to 0x00. In the precharge state, charge current into the battery is I_PRECHG.

The following events cause the state machine to exit this state:

• Battery voltage rises above V_PRECHG and the charger enters the next state in the charging cycle: Trickle Charge.
• If the battery charger remains in this state for longer than t_PQ, the charger state machine transitions to the Timer Fault state.
• If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state.

Note that the precharge state works with battery voltages down to 0V. The 0V operation typically allows this battery charger to recover batteries that have an open internal pack protector. Typically, a battery pack's internal protection circuit opens if the battery has seen an overcurrent, undervoltage, or overvoltage. When a battery with an open internal pack protector is used with this charger, the precharge mode current flows into the 0V battery; this current raises the pack’s terminal voltage to the level where the internal pack protection switch closes.

Note that a normal battery typically stays in the precharge state for several minutes or less. Therefore a battery that stays in the precharge for longer than t_PQ might be experiencing a problem.

As shown in Figure 2, the charger state machine is in trickle charge state when  V_PRECHG< V_BATT < V_SYSMIN - 500mV. After being in this state for t_SCIDG, a CHG_I interrupt is generated if CHG_OK was 0 previously, CHG_OK is set to 1 and CHG_DTLS = 0x00.

With PQEN = 1 (default) and the MAX77960/MAX77961 are in the trickle charge state, the current in the battery is less than or equal to ITRICKLE. When PQEN = 0, the charger skips trickle charge state and transitions directly to fast charge state and the battery charging current is less than or equal to I_FC.

Charge current may be less than I_TRICKLE/I_FC for any of the following reasons:

• The charger input is in input current limit.
• The charger input voltage is low.
• The charger is in thermal foldback.
• The system load is consuming adapter current. Note that the system load always gets priority over the battery charge current.

Typical systems operate with PQEN = 1. When operating with PQEN = 0, the system’s software usually sets I_FC to a low value such as 200mA and then monitors the battery voltage. When the battery exceeds a relatively low voltage such as 6V, then the system’s software usually increases I_FC.

The following events cause the state machine to exit this state:

• When the battery voltage rises above V_SYSMIN - 500mV or the PQEN bit is cleared, the charger enters the next state in the charging cycle: Fast Charge (CC).
• If the battery charger remains in this state for longer than t_PQ, the charger state machine transitions to the Timer Fault state.
• If the watchdog timer is not serviced, the charger state machine transitions to the Watchdog Suspend state.

Note that a normal battery typically stays in the trickle charge state for several minutes or less. Therefore, a battery that stays in trickle charge for longer than t_PQ might be experiencing a problem.

As shown in Figure 2, the charger enters the fast-charge constant current (CC) state when V_SYSMIN - 500mV (typ) < V_BATT < V_BATTREG. After being in the fast-charge CC state for t_SCIDG, a CHG_I interrupt is generated if CHG_OK was 0 previously, CHG_OK is set to 1 and CHG_DTLS = 0x01.

In the fast-charge CC state, the battery charging current is less than or equal to I_FC. Charge current can be less than I_FC for any of the following reasons:

• The charger input is in input current limit.
• The charger input voltage is low.
• The charger is in thermal foldback.
• The system load is consuming adapter current. Note that the system load always gets priority over the battery charging current.

The following events cause the state machine to exit this state:

• When the battery voltage rises above V_BATTREG, the charger enters the next state in the charging cycle: Fast Charge (CV).
• If the battery charger remains in this state for longer than t_FC, the charger state machine transitions to the Timer Fault state.
• If the watchdog timer is not serviced, the charger state machine transitions to the Watchdog Suspend state.

The battery charger dissipates the most power in the fast-charge constant current state, which causes the die temperature to rise. If the die temperature exceeds T_REG, the thermal foldback loop is engaged and I_FC is reduced. See the Thermal Foldback section for more information.

As shown in Figure 2, the charger enters the fast-charge constant voltage (CV) state when the battery voltage rises to V_BATTREG from the fast-charge CC state. After being in the fast-charge CV state for t_SCIDG, a CHG_I interrupt is generated if CHG_OK was 0 previously, CHG_OK is set to 1 and CHG_DTLS = 0x02.

In the fast-charge CV state, the battery charger maintains V_BATTREG across the battery and the charge current is less than or equal to I_FC. As shown in Figure 1, charger current decreases exponentially in this state as the battery becomes fully charged.

The smart power selector control circuitry can reduce the charge current for any of the following reasons:

• The charger input is in input current limit.
• The charger input voltage is low.
• The charger is in thermal foldback.
• The system load is consuming adapter current. Note that the system load always gets priority over the battery charge current.

The following events cause the state machine to exit this state:

• When the charger current is below I_TO for t_TERM, the charger enters the Top-Off State.
• If the battery charger remains in this state for longer than t_FC, the charger state machine transitions to the Timer Fault State.
• If the watchdog timer is not serviced, the charger state machine transitions to the Watchdog Timer Suspend State.

As shown in Figure 2, the top-off state can only be entered from the fast-charge CV state when the charger current decreases below I_TO for t_TERM. After being in the top-off state for t_SCIDG, a CHG_I interrupt is generated if CHG_OK was 0 previously, CHG_OK is set to 1, and CHG_DTLS = 0x03. In the top-off state the battery charger maintains V_BATTREG across the battery and typically the charge current is less than or equal to I_TO.

The smart power selector control circuitry can reduce the charge current for any of the following reasons:

• The charger input is in input current limit.
• The charger input voltage is low.
• The charger is in thermal foldback.
• The system load is consuming adapter current. Note that the system load always gets priority over the battery charge current.

The following events cause the state machine to exit this state:

• After being in this state for the top-off time (t_TO), the charger enters the Done State.
• If V_BATT < V_BATTREG - V_RSTRT, the charger goes back to the Fast-Charge Constant Current State.
• If the watchdog timer is not serviced, the charger state machine transitions to the Watchdog Timer Suspend State.

As shown in Figure 2, the battery charger enters its done state after the charger has been in the top-off state for t_TO. After being in this state for t_SCIDG, a CHG_I interrupt is generated only if CHG_OK was 0 previously, CHG_OK is set to 0 and CHG_DTLS = 0x04.

The following events cause the state machine to exit this state:

• If V_BATT < V_BATTREG - V_RSTRT, the charger goes back to the Fast-Charge Constant Current State.
• If the watchdog timer is not serviced, the charger state machine transitions to the Watchdog Timer Suspend State.

In the done state, the battery charging current (I_CHG) is 0A and the charger presents a very low load (I_MBDN) to the battery. If the system load presented to the battery is low (<< 100µA), then a typical system can remain in the done state for many days. If left in the done state long enough, the battery voltage decays below the charging restart threshold (V_RSTRT) and the charger state machine transitions back into the fast-charge CC state. There is no soft-start (di/dt limiting) during the done to fast-charge state transition.

The battery charger provides both a charge timer and a watchdog timer to ensure safe charging. As shown in Figure 2, the charge timer prevents the battery from charging indefinitely. The time that the charger is allowed to remain in its prequalification states is t_PQ. The time that the charger is allowed to remain in the fast-charge CC and CV states is t_FC, which is programmable with FCHGTIME. Finally the time that the charger is in the top-off state is t_TO which is programmable with TO_TIME. Upon entering the timer fault state a CHG_I interrupt is generated without a delay, CHG_OK is cleared and CHG_DTLS = 0x06.

The charger is off in the timer fault state. The charger can exit the timer fault state when the charger is programmed to be off then on again through the MODE bits or when DISQBAT pin is toggled from L-H-L. Alternatively, the charger input can be removed and reinserted to exit the timer fault state (see the ANY STATE bubble in Figure 2).

The battery charger provides both a charge timer and a watchdog timer to ensure safe charging. As shown in Figure 2, the watchdog timer protects the battery from charging indefinitely in the event that the host hangs or otherwise cannot communicate correctly. The watchdog timer is disabled by default with WDTEN = 0. Enable the feature by setting WDTEN = 1. With watchdog timer enabled, the host controller must reset the watchdog timer within the timer period (t_WD) in order for the charger to operate properly. Reset the watchdog timer by programming WDTCLR = 0x01.

If the watchdog timer expires, charging stops, a CHG_I interrupt is generated if CHG_OK was 1 previously, CHG_OK is cleared, and CHG_DTLS indicates that the charger is off because the watchdog timer expired. Once the watchdog timer expires, the charger can be restarted by programming WDTCLR = 0x01. The SYS node can be supported by the battery and/or the adapter through the DC-DC buck while the watchdog timer is expired.

As shown in Figure 2, the state machine enters the thermal shutdown state when the junction temperature (T_J) exceeds the device’s thermal shutdown threshold (T_SHDN). When T_J is close to T_SHDN, the charger would have already folded back the input current to 0A, (see the Thermal Foldback section for more details), so the charger and the DC-DC are effectively off. Upon entering this state, CHG_I interrupt is generated if CHG_OK was 1 previously, CHG_OK is cleared, and CHG_DTLS = 0x0A.

In the thermal shutdown state, the charger is off. MODE register (CHG_CNFG_00[3:0]) is reset to its default value as well as all O type registers.

The MAX77960/MAX77961 charger use several thermal management techniques to prevent excessive battery and die temperatures.

Thermal foldback maximizes the battery charge current while regulating the MAX77960/MAX77961 junction temperature. As shown in Figure 3, when the die temperature exceeds the value programmed by REGTEMP (T_REG), a thermal limiting circuit reduces the battery charger’s target current by 5%/°C (A_TJREG) with an analog control loop. When the charger transitions in and out of the thermal foldback loop, a CHG_I interrupt is generated and the host microprocessor can read the status of the thermal regulation loop with the TREG status bit. Note that an active thermal foldback loop is not an abnormal operation and the thermal foldback loop status does not affect the CHG_OK bit (only information contained within CHG_DTLS affects CHG_OK).

The MAX77960/MAX77961 safely charge Li+ batteries in accordance with JEITA specifications. The MAX77960/MAX77961 monitor the battery temperature with a NTC thermistor connected at THM pin and automatically adjust the fast-charge current and/or charge termination voltage as the battery temperature varies. JEITA-controlled charging can be disabled by setting JEITA_EN to 0. CHG_DTLS and THM_DTLS registers report JEITA-controlled charging status.

The JEITA controlled fast-charging current (I_{CHGCC_JEITA}) and charge termination voltage (V_{CHGCV_JEITA}) for  T_COLD < T < T_COOL are programmable with I²C bits I_{CHGCC_COOL} and V_{CHGCV_COOL}.

​The charge termination voltage for T_WARM < T < T_HOT is reduced to (CHG_CV_PRM - 180mV/cell), as shown in Figure 4.

Charging is suspended when the battery temperature is too cold or too hot (T < T_COLD or T_HOT < T).

Temperature thresholds (T_COLD, T_COOL, T_WARM, and T_HOT) depend on the thermistor selection. See the Thermistor Input (THM) section for more details.

When battery charge current is reduced by 50%, the charger timer is doubled.

The MAX77960/MAX77961 have a die temperature sensing circuit. When the die temperature exceeds the thermal shutdown threshold, T_SHDN, the MAX77960/MAX77961 shut down and reset O type I²C registers. There is a 15°C thermal hysteresis. After thermal shutdown, if the die temperature reduces by 15°C, the thermal shutdown bus deasserts and the devices reenable. The battery charger has an independent thermal regulation loop. See the Thermal Shutdown State section for more details.

The MAX77960/MAX77961 support factory ship mode with low battery quiescent current, I_SHDN.

When the input source is not valid, and the device is powered by battery, the devices enter factory ship mode if DISQBAT is pulled high or FSHIP_MODE bit is set to 1. I²C communication is unavailable in factory ship mode. When a valid input source is applied to the device's CHGIN pin, the devices exit factory ship mode. I²C communication is enabled, charging is enabled if all conditions to charge are met (e.g., DISQBAT pin is pulled low and MODE[3:0] = 0x05).

The system voltage is regulated to the minimum SYS voltage (V_SYSMIN) when the battery is low (V_BATT < V_SYSMIN - 500mV).

• The charging current is I_PRECHG when V_BATT < V_PRECHG.
• The charging current is I_TRICKLE when V_PRECHG < V_BATT < V_SYSMIN - 500mV.
• The charging current is I_FC when V_SYSMIN - 500mV < V_BATT.

BAT_SP and BAT_SN are differential remote voltage sense lines for the battery. The MAX77960/MAX77961's remote sensing feature improves accuracy and decreases charging time. The thermistor voltage is interpreted with respect to BAT_SN. For best results, connect BATSP and BATSN as close as possible to the battery connector.

Excessive battery discharge current can occur for several reasons such as exposure to moisture, a software problem, an IC failure, a component failure, or a mechanical failure that causes a short circuit. The battery overcurrent alert feature is enabled with B2SOVRC[3:0]; disabling this feature reduces the battery current consumption by I_BOVRC.

When the battery (BATT) to system (SYS) discharge current (I_BATT) exceeds the programmed overcurrent threshold for at least t_BOVRC, the Q_BAT switch closes to reduce the power loss in the MAX77960/MAX77961. A B2SOVRC_I and a BAT_I interrupt are generated, BAT_OK is cleared, and BAT_DTLS reports an overcurrent condition. Typically, when the host processor detects this overcurrent interrupt, it executes a housekeeping routine that tries to mitigate the overcurrent situation. If the processor cannot correct the overcurrent within t_OCP, then the MAX77960/MAX77961 turn off the DC-DC.

t_OCP time duration can be set through the B2SOVRC_DTC register bit (Battery to SYS Overcurrent Debounce Time Control): 0x0 (dflt): t_OCP = 6ms, 0x1: t_OCP = 100ms.

​

INOKB is an open-drain and active-low output that indicates CHGIN power-OK status.

When OTG mode is disabled, (OTGEN = low and MODE[3:0] ≠ 0x0A), INOKB pulls low when a valid input source is inserted at CHGIN, V_{CHGIN_UVLO} < V_CHGIN < V_{CHGIN_OVLO}.

When OTG mode is enabled, (OTGEN = high or MODE[3:0] = 0x0A), INOKB pulls low to indicate the OTG output power OK when V_CHGIN.OTG.UV < V_CHGIN < V_CHGIN.OTG.OV.

INOKB can be used as a logic output by adding a 200kΩ pullup resistor to a system IO voltage.

INOKB can be also used as a LED indicator driver by adding a current limiting resistor and a LED to a pullup voltage source.

STAT is an open-drain and active-low output that indicates charge status. STAT can be used as a logic input to the host processor by adding a 200kΩ pullup resistor to a system IO rail and a rectifier (a diode and a capacitor).

The DC-DC converter topology of the MAX77960/MAX77961 allows it to operate as a forward buck-boost converter or as a reverse buck converter. The modes of the DC-DC converter are controlled with MODE[3:0] register bits. When MODE[3:0] = 0x0A or OTGEN = high, the DC-DC converter operates in reverse buck mode, allowing it to source current to CHGIN, commonly referred to as USB OTG mode.

In OTG mode, the DC-DC converter operates in reverse buck mode and regulates V_CHGIN to V_CHGIN.OTG (5.1V typ). The current through the CHGIN current-sensing resistor (CSINN, CSINP) is limited to the value programmed by OTG_ILIM[2:0]. There are eight OTG_ILIM options to program CHGIN current limit from 500mA to 3A. When the OTG mode is enabled, the unipolar CHGIN transfer function measures current going out of CHGIN. When OTG mode is disabled, the unipolar CHGIN transfer function measures current going into CHGIN.

OTG_I, OTG_M, OTG_OK are the interrupt bit, interrupt mask bit and interrupt status bit associated with OTG function. OTG_DTLS[1:0] reports the status of the OTG operation. OTG_DTLS[1:0] is latched until the host reads the register.

If the external OTG load at CHGIN exceeds ICHGIN.OTG.ILIM current limit for a minimum of 37.5ms, an OTG_I interrupt is generated, OTG_OK = 0 and OTG_DTLS[1:0] = 01. The reverse buck operates as a current limited voltage source when overloaded. The DC-DC converter stops switching when the OTG_ILIM condition lasts for 60ms and automatically resumes switching after 300ms off time. If the OTG_ILIM fault condition at CHGIN persists, the DC-DC toggles on and off with ~60ms on and ~300ms off.

When CHGIN voltage drops below V_{CHGIN.OTG.UVLO}, the DC-DC stops switching and an OTG_I interrupt is generated. OTG_OK = 0 and OTG_DTLS[1:0] = 00.

When CHGIN voltage exceeds V_CHGIN.OTG.OV, the DC-DC stops switching and an OTG_I interrupt is generated. OTG_OK = 0 and OTG_DTLS[1:0] = 10.

If the DC-DC stops switching due to a OTG_UV or OTG_OV fault condition, it automatically retries after 300ms off time.

INOKB is the hardware indication of the OTG power good. See the Input Power-OK/OTG Power-OK Output (INOKB) section for details.

The OTGEN is an active high input. When OTGEN pin is pulled high, the OTG function is enabled. When the OTGEN pin is pulled low, the OTG function can be enabled through I²C by setting MODE[3:0] = 0x0A. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ.

The devices enable reverse buck operation only when the voltage on the CHGIN bypass cap, V_CHGIN, falls below V_{CHGIN_UVLO}.

In case V_CHGIN is above V_{CHGIN_UVLO} threshold at the OTG enable, the devices ensure V_CHGIN node discharge through a 8kΩ pulldown resistor before enabling the OTG function and reverse buck switching.

Pulldown is released once V_{CHGIN_UVLO} is reached.

AVL is the power input for the MAX77960/MAX77961’s analog circuitry. Do not power external devices from this pin. Bypass with a 4.7Ω resistor between AVL and PVL and a 4.7μF capacitor from AVL to GND.

PVL is an internal 1.8V LDO output that powers the MAX77960/MAX77961’s low-side gate driver circuitry. Do not power external devices other than pullup resistors from this pin. Bypass with a 4.7μF capacitor to GND.

V_SYS Fault

The MAX77960/MAX77961 monitor the V_SYS node for undervoltage and overvoltage events. The following sections describe the devices' behavior if any of these events is to occur.

V_SYS Undervoltage Lockout (V_SYSUVLO)

When the voltage from SYS to GND (V_SYS) is less than the undervoltage lockout threshold (V_SYSUVLO), the MAX77960/MAX77961 generate a SYSUVLO_I interrupt immediately. If V_SYS is undervoltage for greater than 8ms, the device shuts down and resets O Type I²C registers.

V_SYS Overvoltage Lockout (V_SYSOVLO)

When the V_SYS exceeds V_SYSOVLO, the MAX77960/MAX77961 generate a SYSOVLO_I interrupt immediately and the device shuts down and resets O Type I²C registers.

Thermal Fault

The MAX77960/MAX77961 have a die temperature sensing circuit. When the die temperature exceeds the thermal shutdown threshold, 165°C (T_SHDN), the MAX77960/MAX77961 shut down and reset O Type I²C registers. There is a 15°C thermal hysteresis. After thermal shutdown, if the die temperature reduces by 15°C, the thermal shutdown bus deasserts and IC reenables. The battery charger has an independent thermal regulation loop. See the Thermal Foldback section for more details.

The INTB is an active-low, open-drain output. Connect a pullup resistor to the pullup power source.

The MAX77960/MAX77961's INTB can be connected to the host's interrupt input and signals to the host when unmasked interrupt events occur within the MAX77960/MAX77961.

The I²C bus is a multimaster bus. The maximum number of devices that can attach to the bus is only limited by bus capacitance.

Figure 6 shows an example of a typical I²C system. A device on I²C bus that sends data to the bus is called a transmitter. A device that receives data from the bus is called a receiver. The device that initiates a data transfer and generates SCL clock signals to control the data transfer is a master. Any device that is being addressed by the master is considered a slave. When the MAX77960/MAX77961 I²C-compatible interface is operating, it is a slave on I²C bus and it can be both a transmitter and a receiver.

One data bit is transferred for each SCL clock cycle. The data on SDA must remain stable during the high portion of SCL clock pulse. Changes in SDA while SCL is high are control signals (START and STOP conditions).

When I²C serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high.

A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission by issuing a NOT ACKNOWLEDGE followed by a STOP condition.

A STOP condition frees the bus. To issue a series of commands to the slave, the master can issue REPEATED START (Sr) commands instead of a STOP command in order to maintain control of the bus. In general, a REPEATED START command is functionally equivalent to a regular START command.

When a STOP condition or incorrect address is detected, the ICs internally disconnect SCL from the I²C serial interface until the next START condition, minimizing digital noise and feed-through.

Both the I²C bus master and the IC (slave) generate acknowledge bits when receiving data. The acknowledge bit is the last bit of each nine bit data packet. To generate an ACKNOWLEDGE (A), the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a NOT-ACKNOWLEDGE (nA), the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time.

The devices provide I²C 3.0-compatible (1MHz) serial interface.

• I²C Revision 3 Compatible Serial Communications Channel
  • 0Hz to 100kHz (standard mode)
  • 0Hz to 400kHz (fast mode)
  • 0Hz to 1MHz (fast-mode plus)
• Does not utilize I²C clock stretching

Operating in standard mode, fast mode, and fast-mode plus does not require any special protocols. The main consideration when changing the bus speed through this range is the combination of the bus capacitance and pullup resistors. Higher time constants created by the bus capacitance and pullup resistance (C x R) slow the bus operation. Therefore, when increasing bus speeds the pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing section of the I²C revision 3.0 specification for detailed guidance on the pullup resistor selection. In general, for bus capacitance of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus needs about a 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω pullup resistors. Note that the pullup resistor dissipates power when the open-drain bus is low. The lower the value of the pullup resistor, the higher the power dissipation (V²/R).

Operating in high-speed mode requires some special considerations. For the full list of considerations, see the I²C 3.0 specification. The major considerations with respect to the IC are:

• I²C bus master uses current source pullups to shorten the signal rise times.
• I²C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus speed.
• The communication protocols need to utilize the high-speed master code.

At power-up and after each STOP condition, the IC input filters are set for standard mode, fast mode, or fast-mode plus (i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the high-speed master code protocols that are described in the Communication Protocols section.

Figure 9 shows the protocol for the I²C master device to write one byte of data to the ICs. This protocol is the same as SMBus specification’s Write Byte protocol.

The Write Byte protocol is as follows:

1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. At the rising edge of SCL, the data byte is loaded into its target register and the data becomes active.
8. The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing a REPEATED START (Sr) leaves the bus input filters in their current state.

Figure 10 shows the protocol for writing to sequential registers. This protocol is similar to the Write Byte protocol, except the master continues to write after it receives the first byte of data. When the master is done writing, it issues a STOP or REPEATED START.

The Writing to Sequential Registers protocol is as follows:

1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. At the rising edge of SCL, the data byte is loaded into its target register and the data becomes active.
8. Steps 6 to 7 are repeated as many times as the master requires.
9. During the last acknowledge related clock pulse, the slave issues an ACKNOWLEDGE (A).
10. The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing a REPEATED START (Sr) leaves the bus input filters in their current state.

Figure 11 shows the protocol for the I²C master device to write multiple bytes to the devices using register data pairs. This protocol allows the I²C master device to address the slave only once and then send data to multiple registers in a random order. Registers can be written continuously until the master issues a STOP condition.

The Multiple Byte Register Data Pair protocol is as follows:

1. The master sends a START command.
2. The master sends the 7-bit slave address followed by a write bit.
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. At the rising edge of SCL, the data byte is loaded into its target register and the data becomes active.
8. Steps 4 to 7 are repeated as many times as the master requires.
9. The master sends a STOP condition. During the rising edge of the stop related SDA edge, the data byte that was previously written is loaded into the target register and becomes active.

The I²C master device reads one byte of data to the devices. This protocol is the same as SMBus specification’s Read Byte protocol.

The Read Byte protocol is as follows:

1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a REPEATED START command (Sr).
7. The master sends the 7-bit slave address followed by a read bit (R/W = 1).
8. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
9. The addressed slave places 8 bits of data on the bus from the location specified by the register pointer.
10. The master issues a NOT-ACKNOWLEDGE (nA).
11. The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing a REPEATED START (Sr) leaves the bus input filters in their current state.