Detailed Description

The MAX20010C/MAX20010D/MAX20010E ICs are high-efficiency, synchronous step-down converters that operate with a 3.0V to 5.5V input voltage range and provide a 0.5V to 1.5875V output voltage range. The ICs deliver up to 6A of load current and achieve ±2% output error over load, line, and temperature ranges. The MAX20010D/MAX20010E offers improved transient performance.

Optional spread-spectrum frequency modulation minimizes radiated electromagnetic emissions due to the switching frequency. The I²C-programmable I/O (SYNC) enables system synchronization.

Integrated low R_DS(ON) switches help improve efficiency at heavy loads and make the layout a much simpler task with respect to discrete solutions. The ICs are offered with a factory-preset output voltage that is dynamically adjustable through the I²C interface. The output voltage can be set to any desired value between 0.5V and 1.27V in 10mV steps, and between 0.625V and 1.5875V in 12.5mV steps.

Additional features include adjustable soft-start, power-good delay, DVS rate, overcurrent, and overtemperature protections (see Figure 1).

The ICs feature an I²C, 2-wire serial interface consisting of a serial-data line (SDA) and serial-clock line (SCL). SDA and SCL facilitate communication between the ICs and the master at clock rates up to 3.4MHz. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus. Figure 2 shows the 2-wire interface timing diagram. A master device communicates with the ICs by transmitting the proper address followed by the data word. Each transmit sequence is framed by a START (S) or Repeated START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.

The SDA line operates as both an input and an open-drain output. A pullup resistor greater than 500Ω is required on the SDA bus. The SCL line operates as an input only. A pullup resistor greater than 500Ω is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. The SCL and SDA inputs suppress noise spikes to assure proper device operation even on a noisy bus.

A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 3).

A START (S) condition from the master signals the beginning of a transmission to the IC. The master terminates transmission, and frees the bus, by issuing a STOP (P) condition. The bus remains active if a Repeated START (Sr) condition is generated instead of a STOP condition.

The acknowledge bit (ACK) is a clocked 9th bit that the ICs use to handshake receipt each byte of data (Figure 4). The device pulls down SDA during the master-generated 9th clock pulse. The SDA line must remain stable and low during the high period of the acknowledge clock pulse. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master can reattempt communication.

 *See the Ordering Information table for the 7-bit default settings for ADDR=0.

A write to the device includes:

• Transmission of a START condition
• Slave address with the write bit set to 0
• 1 byte of data to the register address
• 1 byte of data to the command register
• STOP condition

(Figure 5 illustrates the proper format for one frame)

A read from the device includes:

• Transmission of a START condition
• Slave address with the write bit set to 0
• 1 byte of data to the register address
• Restart condition
• Slave address with the read bit set to 1
• 1 byte of data to the command register
• STOP condition

(Figure 5 illustrates the proper format for one frame)

Figure 6 shows the protocol for the I²C master device to write 1 byte of data to the ICs. This protocol is the same as the SMBus specification’s “write byte” protocol.

The “write byte” protocol is as follows:

1. Master sends a START command (S).
2. Master sends the 7-bit slave address followed by awrite bit (R/W = 0).
3. Addressed slave asserts an acknowledge (A) by pulling SDA low.
4. Master sends an 8-bit register pointer.
5. Slave acknowledges the register pointer.
6. Master sends a data byte.
7. Slave updates with the new data.
8. Slave acknowledges or not acknowledges the databyte. The next rising edge on SDA loads the data byteinto its target register and the data becomes active.
9. Master sends a STOP condition (P) or a RepeatedSTART condition (Sr).

Figure 7 shows the protocol for the I²C master device to write multiple bytes to the ICs using register-data pairs. This protocol allows the I²C master device to address the slave only once and then send data to multiple registers in a random order. Registers can be written continuously until the master issues a STOP condition.

The “multiple byte register-data pair” protocol is as follows:

1. Master sends a START command.
2. Master sends the 7-bit slave address followed by a write bit.
3. Addressed slave asserts an acknowledge by pulling SDA low.
4. Master sends an 8-bit register pointer.
5. Save acknowledges the register pointer.
6. Master sends a data byte.
7. Slave acknowledges the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active.
8. Steps 4–7 are repeated as many times as the master requires.
9. Master sends a STOP condition. During the rising edge of the stop-related SDA edge, the data byte that was previously written is loaded into the target register and becomes active.

The current-limit feature protects the ICs against short-circuit and overload conditions at the output. After soft-start is completed, if V_OUT is less than 50% of the set value and the IC is in current limit, the IC shuts off for 4ms (at 2.2MHz switching frequency) and repeats soft-start. This cycle repeats until the short or overload condition is removed. See the short-circuit (PWM) waveform for an example.

*Note: Reserved registers and bits are not used for readback; they are reserved for internal use.

*Note: VSTEP = ‘0’; when VSTEP = ‘1’, increase by a factor of 1.25.